feat(testbench): add sequential circuit testbench generation

Summary

• Add sequential testbench generation: clock/reset detection, per-cycle vectors, and Verilog stimulus/clock blocks
• Extend TestbenchGenerator API (SequentialTestVector, generateSequentialTestVectors, helpers) with bilingual Doxygen
• Document sequential testbench usage in docs/*/Sequential.md and cover with SequentialTestbench tests

Test plan

• ctest --preset=dev (214/214 passed after rebase onto current main)
• Spot-check generated sequential .v testbench for FF and latch examples
• Optional: run Icarus-backed SequentialTestbench.SequentialIcarusVerification when iverilog/vvp are available